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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] - Rev 360

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Rev Log message Author Age Path
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5015d 13h /openrisc/trunk/orpsocv2/sim/bin/
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests
julius 5016d 07h /openrisc/trunk/orpsocv2/sim/bin/
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.
julius 5017d 13h /openrisc/trunk/orpsocv2/sim/bin/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5018d 13h /openrisc/trunk/orpsocv2/sim/bin/
348 First stage of ORPSoCv2 update - more to come julius 5018d 17h /openrisc/trunk/orpsocv2/sim/bin/
78 Fixed typo in Silos workaround script rherveille 5171d 12h /openrisc/trunk/orpsocv2/sim/bin/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour
rherveille 5171d 13h /openrisc/trunk/orpsocv2/sim/bin/
76 Added: +libext+.v
Added: +incdir+.
rherveille 5172d 12h /openrisc/trunk/orpsocv2/sim/bin/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5219d 02h /openrisc/trunk/orpsocv2/sim/bin/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5219d 03h /openrisc/trunk/orpsocv2/sim/bin/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5221d 19h /openrisc/trunk/orpsocv2/sim/bin/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5221d 22h /openrisc/trunk/orpsocv2/sim/bin/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5241d 20h /openrisc/trunk/orpsocv2/sim/bin/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5248d 21h /openrisc/trunk/orpsocv2/sim/bin/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5258d 18h /openrisc/trunk/orpsocv2/sim/bin/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5300d 14h /openrisc/trunk/orpsocv2/sim/bin/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5305d 18h /openrisc/trunk/orpsocv2/sim/bin/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5316d 10h /openrisc/trunk/orpsocv2/sim/bin/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5326d 18h /openrisc/trunk/orpsocv2/sim/bin/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5344d 18h /openrisc/trunk/orpsocv2/sim/bin/

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