URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] - Rev 53

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5364d 18h	/openrisc/trunk/orpsocv2/sim/bin/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5379d 16h	/openrisc/trunk/orpsocv2/sim/bin/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5398d 10h	/openrisc/trunk/orpsocv2/sim/bin/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5449d 21h	/openrisc/trunk/orpsocv2/sim/bin/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5473d 18h	/openrisc/trunk/orpsocv2/sim/bin/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5489d 14h	/openrisc/trunk/orpsocv2/sim/bin/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5493d 21h	/openrisc/trunk/orpsocv2/sim/bin/
36	Better clean rule in makefile	julius	5507d 22h	/openrisc/trunk/orpsocv2/sim/bin/
6	Checking in ORPSoCv2	julius	5512d 09h	/openrisc/trunk/orpsocv2/sim/bin/