| Rev |
Log message |
Author |
Age |
Path |
| 484 |
ORPSoC update - adding ability to use a Modelsim without vopt executable |
julius |
5032d 02h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5041d 17h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5041d 20h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5046d 21h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5073d 11h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5087d 06h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
5093d 13h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5100d 06h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
5112d 17h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5115d 10h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5117d 16h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
5120d 15h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5165d 22h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5167d 07h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5167d 12h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5168d 06h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5169d 12h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5170d 12h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5170d 16h |
/openrisc/trunk/orpsocv2/sim/bin/ |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5323d 11h |
/openrisc/trunk/orpsocv2/sim/bin/ |
