OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] - Rev 57

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5348d 00h /openrisc/trunk/orpsocv2/sim/bin/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5358d 16h /openrisc/trunk/orpsocv2/sim/bin/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5368d 23h /openrisc/trunk/orpsocv2/sim/bin/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5387d 00h /openrisc/trunk/orpsocv2/sim/bin/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5401d 22h /openrisc/trunk/orpsocv2/sim/bin/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5420d 16h /openrisc/trunk/orpsocv2/sim/bin/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5472d 03h /openrisc/trunk/orpsocv2/sim/bin/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5496d 00h /openrisc/trunk/orpsocv2/sim/bin/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5511d 21h /openrisc/trunk/orpsocv2/sim/bin/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5516d 03h /openrisc/trunk/orpsocv2/sim/bin/
36 Better clean rule in makefile julius 5530d 04h /openrisc/trunk/orpsocv2/sim/bin/
6 Checking in ORPSoCv2 julius 5534d 15h /openrisc/trunk/orpsocv2/sim/bin/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.