| Rev |
Log message |
Author |
Age |
Path |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5006d 06h |
/openrisc/trunk/orpsocv2/sw/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5006d 07h |
/openrisc/trunk/orpsocv2/sw/ |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5006d 15h |
/openrisc/trunk/orpsocv2/sw/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5007d 01h |
/openrisc/trunk/orpsocv2/sw/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5008d 06h |
/openrisc/trunk/orpsocv2/sw/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5009d 07h |
/openrisc/trunk/orpsocv2/sw/ |
| 349 |
ORPSoCv2 update with new software and makefile update |
julius |
5009d 11h |
/openrisc/trunk/orpsocv2/sw/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5009d 11h |
/openrisc/trunk/orpsocv2/sw/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5212d 16h |
/openrisc/trunk/orpsocv2/sw/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5232d 14h |
/openrisc/trunk/orpsocv2/sw/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5249d 12h |
/openrisc/trunk/orpsocv2/sw/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5291d 08h |
/openrisc/trunk/orpsocv2/sw/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5350d 10h |
/openrisc/trunk/orpsocv2/sw/ |
| 50 |
Adding or32_funcs.S |
julius |
5350d 14h |
/openrisc/trunk/orpsocv2/sw/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5369d 04h |
/openrisc/trunk/orpsocv2/sw/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5384d 15h |
/openrisc/trunk/orpsocv2/sw/ |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5391d 15h |
/openrisc/trunk/orpsocv2/sw/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5420d 15h |
/openrisc/trunk/orpsocv2/sw/ |
| 6 |
Checking in ORPSoCv2 |
julius |
5483d 03h |
/openrisc/trunk/orpsocv2/sw/ |
