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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 420

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Rev Log message Author Age Path
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4979d 12h /openrisc/trunk/orpsocv2/sw/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4983d 02h /openrisc/trunk/orpsocv2/sw/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4983d 14h /openrisc/trunk/orpsocv2/sw/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4984d 14h /openrisc/trunk/orpsocv2/sw/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4985d 02h /openrisc/trunk/orpsocv2/sw/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4986d 08h /openrisc/trunk/orpsocv2/sw/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4988d 13h /openrisc/trunk/orpsocv2/sw/
396 ORPSoCv2 final software fixes...for now. See updated README julius 4991d 12h /openrisc/trunk/orpsocv2/sw/
395 ORPSoCv2 moving ethernet tests to correct place julius 4991d 13h /openrisc/trunk/orpsocv2/sw/
394 ORPSoCv2 removing unused directories julius 4991d 13h /openrisc/trunk/orpsocv2/sw/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4991d 13h /openrisc/trunk/orpsocv2/sw/
392 ORPSoCv2 software path reorganisation stage 1. julius 4992d 05h /openrisc/trunk/orpsocv2/sw/
374 ORPSoCv2 adding some files forgotten from last checkin julius 5024d 12h /openrisc/trunk/orpsocv2/sw/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5024d 12h /openrisc/trunk/orpsocv2/sw/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5036d 19h /openrisc/trunk/orpsocv2/sw/
361 OPRSoCv2 - adding things left out in last check-in julius 5038d 09h /openrisc/trunk/orpsocv2/sw/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5038d 09h /openrisc/trunk/orpsocv2/sw/
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5038d 18h /openrisc/trunk/orpsocv2/sw/
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5039d 04h /openrisc/trunk/orpsocv2/sw/
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5040d 09h /openrisc/trunk/orpsocv2/sw/

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