URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 61

Rev	Log message	Author	Age	Path
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5325d 06h	/openrisc/trunk/orpsocv2/sw/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5384d 09h	/openrisc/trunk/orpsocv2/sw/
50	Adding or32_funcs.S	julius	5384d 13h	/openrisc/trunk/orpsocv2/sw/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5403d 02h	/openrisc/trunk/orpsocv2/sw/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5418d 14h	/openrisc/trunk/orpsocv2/sw/
45	Orpsoc eth test fix and script error message update	julius	5425d 13h	/openrisc/trunk/orpsocv2/sw/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5454d 13h	/openrisc/trunk/orpsocv2/sw/
6	Checking in ORPSoCv2	julius	5517d 01h	/openrisc/trunk/orpsocv2/sw/