OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 64

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5260d 11h /openrisc/trunk/orpsocv2/sw/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5302d 07h /openrisc/trunk/orpsocv2/sw/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5361d 09h /openrisc/trunk/orpsocv2/sw/
50 Adding or32_funcs.S julius 5361d 13h /openrisc/trunk/orpsocv2/sw/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5380d 03h /openrisc/trunk/orpsocv2/sw/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5395d 14h /openrisc/trunk/orpsocv2/sw/
45 Orpsoc eth test fix and script error message update julius 5402d 14h /openrisc/trunk/orpsocv2/sw/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5431d 14h /openrisc/trunk/orpsocv2/sw/
6 Checking in ORPSoCv2 julius 5494d 02h /openrisc/trunk/orpsocv2/sw/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.