URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [apps/] [dhry/] - Rev 356

Rev	Log message	Author	Age	Path
356	Added new simple MAC test to ORPSoC test suite: * orpsocv2/sw/or1200asm/or1200asm-mac.S: Added Fixed MAC pipeline issue in OR1200 * or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn. * orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: "" * orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version * orpsocv2/sim/bin/Makefile: Added new MAC test to default tests	julius	5040d 22h	/openrisc/trunk/orpsocv2/sw/apps/dhry/
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5042d 03h	/openrisc/trunk/orpsocv2/sw/apps/dhry/
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5325d 04h	/openrisc/trunk/orpsocv2/sw/apps/dhry/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5403d 01h	/openrisc/trunk/orpsocv2/sw/apps/dhry/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5454d 11h	/openrisc/trunk/orpsocv2/sw/apps/dhry/
6	Checking in ORPSoCv2	julius	5517d 00h	/openrisc/trunk/orpsocv2/sw/apps/dhry/