URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [board/] - Rev 630

Rev	Log message	Author	Age	Path
506	ORPSoC or1200 interrupt and syscall generation test	julius	4976d 17h	/openrisc/trunk/orpsocv2/sw/board/
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5031d 23h	/openrisc/trunk/orpsocv2/sw/board/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5126d 13h	/openrisc/trunk/orpsocv2/sw/board/
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5131d 18h	/openrisc/trunk/orpsocv2/sw/board/