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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] - Rev 571

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Rev Log message Author Age Path
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5054d 00h /openrisc/trunk/orpsocv2/sw/bootrom/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5123d 14h /openrisc/trunk/orpsocv2/sw/bootrom/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5130d 10h /openrisc/trunk/orpsocv2/sw/bootrom/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5135d 15h /openrisc/trunk/orpsocv2/sw/bootrom/
361 OPRSoCv2 - adding things left out in last check-in julius 5182d 11h /openrisc/trunk/orpsocv2/sw/bootrom/

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