URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] - Rev 807

Rev	Log message	Author	Age	Path
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4891d 17h	/openrisc/trunk/orpsocv2/sw/bootrom/
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4961d 08h	/openrisc/trunk/orpsocv2/sw/bootrom/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4968d 03h	/openrisc/trunk/orpsocv2/sw/bootrom/
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	4973d 08h	/openrisc/trunk/orpsocv2/sw/bootrom/
361	OPRSoCv2 - adding things left out in last check-in	julius	5020d 04h	/openrisc/trunk/orpsocv2/sw/bootrom/