| Rev |
Log message |
Author |
Age |
Path |
| 672 |
ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled
OR1200 RTL fix and software test added. |
julius |
4556d 17h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 671 |
ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model |
julius |
4556d 17h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 655 |
ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation |
julius |
4607d 19h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 619 |
ORPSoC OR1200 fix and regression test for bug 51.
signed-off Julius Baxter
reviewed by Stefan Kristiansson |
julius |
4688d 19h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 567 |
ORPSoC ethmac test and diagnosis software program updates. |
julius |
4720d 08h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 535 |
ORPSoC - adding sw tests for l.rfe |
julius |
4779d 21h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4787d 06h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4813d 00h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4829d 21h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4832d 21h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4834d 17h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4837d 04h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4861d 03h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4861d 04h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4868d 06h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4886d 10h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4888d 10h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4889d 06h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
4895d 10h |
/openrisc/trunk/orpsocv2/sw/tests/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4896d 09h |
/openrisc/trunk/orpsocv2/sw/tests/ |
