URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [ethmac/] - Rev 412

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	4982d 12h	/openrisc/trunk/orpsocv2/sw/tests/ethmac/
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	4983d 12h	/openrisc/trunk/orpsocv2/sw/tests/ethmac/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	4984d 01h	/openrisc/trunk/orpsocv2/sw/tests/eth/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4985d 06h	/openrisc/trunk/orpsocv2/sw/tests/eth/
395	ORPSoCv2 moving ethernet tests to correct place	julius	4990d 11h	/openrisc/trunk/orpsocv2/sw/tests/eth/