OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [ethmac/] - Rev 745

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
567 ORPSoC ethmac test and diagnosis software program updates. julius 4887d 07h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4954d 05h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 5004d 02h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5053d 08h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5094d 23h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 5101d 14h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 5114d 14h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5122d 23h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 5127d 01h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 5128d 01h /openrisc/trunk/orpsocv2/sw/tests/ethmac/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5128d 13h /openrisc/trunk/orpsocv2/sw/tests/eth/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5129d 19h /openrisc/trunk/orpsocv2/sw/tests/eth/
395 ORPSoCv2 moving ethernet tests to correct place julius 5135d 00h /openrisc/trunk/orpsocv2/sw/tests/eth/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.