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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [uart/] - Rev 594

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Rev Log message Author Age Path
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5089d 08h /openrisc/trunk/orpsocv2/sw/tests/uart/
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 5102d 07h /openrisc/trunk/orpsocv2/sw/tests/uart/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 5108d 23h /openrisc/trunk/orpsocv2/sw/tests/uart/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5122d 23h /openrisc/trunk/orpsocv2/sw/tests/uart/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5126d 10h /openrisc/trunk/orpsocv2/sw/tests/uart/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5129d 09h /openrisc/trunk/orpsocv2/sw/tests/uart/

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