URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [utils/] - Rev 132

Rev	Log message	Author	Age	Path
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5375d 18h	/openrisc/trunk/orpsocv2/sw/utils/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5412d 15h	/openrisc/trunk/orpsocv2/sw/utils/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5547d 18h	/openrisc/trunk/orpsocv2/sw/utils/
45	Orpsoc eth test fix and script error message update	julius	5554d 18h	/openrisc/trunk/orpsocv2/sw/utils/
6	Checking in ORPSoCv2	julius	5646d 06h	/openrisc/trunk/orpsocv2/sw/utils/