OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [utils/] - Rev 788

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
673 Multiple 64-bit fixes (mostly sign and size of constants). Fix bug #1. yannv 4717d 08h /openrisc/trunk/orpsocv2/sw/utils/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5032d 13h /openrisc/trunk/orpsocv2/sw/utils/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5120d 07h /openrisc/trunk/orpsocv2/sw/utils/
361 OPRSoCv2 - adding things left out in last check-in julius 5179d 04h /openrisc/trunk/orpsocv2/sw/utils/
349 ORPSoCv2 update with new software and makefile update julius 5182d 08h /openrisc/trunk/orpsocv2/sw/utils/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5385d 13h /openrisc/trunk/orpsocv2/sw/utils/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5422d 10h /openrisc/trunk/orpsocv2/sw/utils/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5557d 13h /openrisc/trunk/orpsocv2/sw/utils/
45 Orpsoc eth test fix and script error message update julius 5564d 13h /openrisc/trunk/orpsocv2/sw/utils/
6 Checking in ORPSoCv2 julius 5656d 01h /openrisc/trunk/orpsocv2/sw/utils/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.