OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] - Rev 1040

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1040 Updated the script. lampret 8014d 05h /or1k/branches/stable_0_1_x/
1039 Added linter directory. lampret 8014d 05h /or1k/branches/stable_0_1_x/
1038 Fixed a typo, reported by Taylor Su. lampret 8014d 07h /or1k/branches/stable_0_1_x/
1037 First import of the new synopsys DC scripts. lampret 8014d 07h /or1k/branches/stable_0_1_x/
1036 Removed old synthesis scripts. lampret 8014d 07h /or1k/branches/stable_0_1_x/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8014d 20h /or1k/branches/stable_0_1_x/
1034 Fixed encoding for l.div/l.divu. lampret 8015d 00h /or1k/branches/stable_0_1_x/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8015d 07h /or1k/branches/stable_0_1_x/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8015d 20h /or1k/branches/stable_0_1_x/
1031 Setting phy to 10Mbps full duplex. simons 8016d 11h /or1k/branches/stable_0_1_x/
1030 Ethernet configured for 10Mbps. simons 8017d 08h /or1k/branches/stable_0_1_x/
1029 Typing error fixed. simons 8017d 09h /or1k/branches/stable_0_1_x/
1028 Import. ivang 8017d 09h /or1k/branches/stable_0_1_x/
1027 PRINTF/printf mess fixed. simons 8017d 17h /or1k/branches/stable_0_1_x/
1026 rtems-20020807 import ivang 8018d 03h /or1k/branches/stable_0_1_x/
1025 PRINTF/printf mess fixed. simons 8018d 06h /or1k/branches/stable_0_1_x/
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 8018d 15h /or1k/branches/stable_0_1_x/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8019d 01h /or1k/branches/stable_0_1_x/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8019d 04h /or1k/branches/stable_0_1_x/
1021 *** empty log message *** rherveille 8023d 06h /or1k/branches/stable_0_1_x/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.