OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] - Rev 1334

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1334 l.ff1 and l.cmov instructions added andreje 7086d 05h /or1k/branches/stable_0_1_x/
1333 gcc 3.4 compile fix phoenix 7097d 00h /or1k/branches/stable_0_1_x/
1332 gcc 3.4.3 compile fix phoenix 7100d 17h /or1k/branches/stable_0_1_x/
1331 jtag bugfix phoenix 7105d 17h /or1k/branches/stable_0_1_x/
1330 jtag bugfix phoenix 7105d 17h /or1k/branches/stable_0_1_x/
1329 Synplify synthesis script first import jcastillo 7110d 04h /or1k/branches/stable_0_1_x/
1327 Firt import of OR1200 over Celoxica RC203 platform jcastillo 7110d 21h /or1k/branches/stable_0_1_x/
1325 Initial import of uClibc-0.9.26 phoenix 7141d 15h /or1k/branches/stable_0_1_x/
1324 memory access functions fixes phoenix 7163d 16h /or1k/branches/stable_0_1_x/
1323 Adrian Wise: or1ksim bugfix & Solaris build phoenix 7164d 22h /or1k/branches/stable_0_1_x/
1322 Christian Krauses bugfixes phoenix 7166d 00h /or1k/branches/stable_0_1_x/
1321 some tests rely on exit(0) as a last std output text to pass phoenix 7167d 15h /or1k/branches/stable_0_1_x/
1320 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7169d 15h /or1k/branches/stable_0_1_x/
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7169d 16h /or1k/branches/stable_0_1_x/
1318 oh well, what a mistake phoenix 7185d 16h /or1k/branches/stable_0_1_x/
1317 CLEAR_GPR change phoenix 7185d 17h /or1k/branches/stable_0_1_x/
1316 added a warning phoenix 7187d 13h /or1k/branches/stable_0_1_x/
1315 missing declaration when defined STACK_ARGS phoenix 7187d 13h /or1k/branches/stable_0_1_x/
1314 in some cases (cbasic test from orp for example) this caused problems, disable for now phoenix 7187d 13h /or1k/branches/stable_0_1_x/
1313 bugfixes jurem 7188d 05h /or1k/branches/stable_0_1_x/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.