OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] - Rev 992

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
992 A bug when cache enabled and bus error comes fixed. simons 8002d 13h /or1k/branches/stable_0_1_x/
991 Different memory controller. simons 8002d 13h /or1k/branches/stable_0_1_x/
990 Test is now complete. simons 8002d 13h /or1k/branches/stable_0_1_x/
989 c++ is making problems so, for now, it is excluded. simons 8003d 21h /or1k/branches/stable_0_1_x/
988 ORP architecture supported. simons 8004d 13h /or1k/branches/stable_0_1_x/
987 ORP architecture supported. simons 8004d 20h /or1k/branches/stable_0_1_x/
986 outputs out of function are not registered anymore markom 8004d 21h /or1k/branches/stable_0_1_x/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8005d 08h /or1k/branches/stable_0_1_x/
984 Disable SB until it is tested lampret 8005d 08h /or1k/branches/stable_0_1_x/
983 First checkin lampret 8005d 10h /or1k/branches/stable_0_1_x/
982 Moved to sim/bin lampret 8005d 10h /or1k/branches/stable_0_1_x/
981 First checkin. lampret 8005d 10h /or1k/branches/stable_0_1_x/
980 Removed sim.tcl that shouldn't be here. lampret 8005d 10h /or1k/branches/stable_0_1_x/
979 Removed old test case binaries. lampret 8005d 10h /or1k/branches/stable_0_1_x/
978 Added variable delay for SRAM. lampret 8005d 10h /or1k/branches/stable_0_1_x/
977 Added store buffer. lampret 8005d 10h /or1k/branches/stable_0_1_x/
976 Added store buffer lampret 8005d 11h /or1k/branches/stable_0_1_x/
975 First checkin lampret 8005d 11h /or1k/branches/stable_0_1_x/
974 Enabled what works on or1ksim and disabled other tests. lampret 8005d 13h /or1k/branches/stable_0_1_x/
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8007d 17h /or1k/branches/stable_0_1_x/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.