URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [MW_0_8_9PRE7/] - Rev 641

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
641	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8210d 15h	/or1k/tags/MW_0_8_9PRE7/
640	Merge profiler and mprofiler with sim.	ivang	8210d 17h	/or1k/tags/MW_0_8_9PRE7/
639	MMU cache inhibit bit test added.	simons	8213d 07h	/or1k/tags/MW_0_8_9PRE7/
638	TLBTR CI bit is now working properly.	simons	8213d 08h	/or1k/tags/MW_0_8_9PRE7/
637	Updated file names.	lampret	8213d 09h	/or1k/tags/MW_0_8_9PRE7/
636	Fixed combinational loops.	lampret	8213d 09h	/or1k/tags/MW_0_8_9PRE7/
635	Fixed Makefile bug.	ivang	8213d 11h	/or1k/tags/MW_0_8_9PRE7/
634	configure.in : fixed to build start/Makefile start.S : l.jalr r9 -> l.jr r9 Added missing files.	ivang	8214d 12h	/or1k/tags/MW_0_8_9PRE7/
633	Bug fix in command line parser.	ivang	8214d 13h	/or1k/tags/MW_0_8_9PRE7/
632	profiler and mprofiler merged into sim.	ivang	8215d 08h	/or1k/tags/MW_0_8_9PRE7/
631	Real cache access is simulated now.	simons	8216d 06h	/or1k/tags/MW_0_8_9PRE7/
630	some bug fixes in store buffer analysis	markom	8216d 15h	/or1k/tags/MW_0_8_9PRE7/
629	typo fixed	markom	8216d 19h	/or1k/tags/MW_0_8_9PRE7/
627	or32 restored	markom	8216d 19h	/or1k/tags/MW_0_8_9PRE7/
626	store buffer added	markom	8216d 20h	/or1k/tags/MW_0_8_9PRE7/
625	Bus error bug fixed. Cache routines added.	simons	8217d 12h	/or1k/tags/MW_0_8_9PRE7/
624	Added logging of writes/read to/from SPR registers.	ivang	8217d 12h	/or1k/tags/MW_0_8_9PRE7/
623	update based on recent changes; arithmetic instructions does not modify carry yet	markom	8217d 14h	/or1k/tags/MW_0_8_9PRE7/
622	Cache test works on hardware.	simons	8217d 17h	/or1k/tags/MW_0_8_9PRE7/
621	Cache test works on hardware.	simons	8217d 18h	/or1k/tags/MW_0_8_9PRE7/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [MW_0_8_9PRE7/] - Rev 641

Filtering Options