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[/] [or1k/] [tags/] [asyst_3/] [or1200/] [rtl/] [verilog/] - Rev 1777

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Rev Log message Author Age Path
1765 root 5601d 11h /or1k/tags/asyst_3/or1200/rtl/verilog/
1237 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7480d 00h /or1k/tags/asyst_3/or1200/rtl/verilog/
1235 Error fixed. simons 7480d 00h /or1k/tags/asyst_3/or1200/rtl/verilog/
1233 Errors fixed. simons 7480d 13h /or1k/tags/asyst_3/or1200/rtl/verilog/
1231 Error fixed. simons 7480d 15h /or1k/tags/asyst_3/or1200/rtl/verilog/
1229 Error fixed. simons 7480d 16h /or1k/tags/asyst_3/or1200/rtl/verilog/
1226 interface to debug changed; no more opselect; stb-ack protocol markom 7483d 03h /or1k/tags/asyst_3/or1200/rtl/verilog/
1225 Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added andreje 7486d 11h /or1k/tags/asyst_3/or1200/rtl/verilog/
1220 Exception prefix configuration changed. simons 7511d 20h /or1k/tags/asyst_3/or1200/rtl/verilog/
1219 Qmem mbist signals fixed. simons 7511d 21h /or1k/tags/asyst_3/or1200/rtl/verilog/
1216 Support for ram with byte selects added. simons 7518d 19h /or1k/tags/asyst_3/or1200/rtl/verilog/
1214 Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. simons 7519d 22h /or1k/tags/asyst_3/or1200/rtl/verilog/
1213 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7524d 10h /or1k/tags/asyst_3/or1200/rtl/verilog/
1210 No functional change. lampret 7524d 10h /or1k/tags/asyst_3/or1200/rtl/verilog/
1209 Fixed instantiation name. lampret 7524d 10h /or1k/tags/asyst_3/or1200/rtl/verilog/
1207 Static exception prefix. lampret 7524d 10h /or1k/tags/asyst_3/or1200/rtl/verilog/
1206 Static exception prefix. lampret 7524d 10h /or1k/tags/asyst_3/or1200/rtl/verilog/
1175 Added three missing wire declarations. No functional changes. lampret 7671d 09h /or1k/tags/asyst_3/or1200/rtl/verilog/
1172 Added embedded memory QMEM. lampret 7673d 18h /or1k/tags/asyst_3/or1200/rtl/verilog/
1171 Added embedded memory QMEM. lampret 7673d 19h /or1k/tags/asyst_3/or1200/rtl/verilog/

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