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[/] [or1k/] [tags/] [nog_patch_37/] [or1ksim/] [cache/] - Rev 1774

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Rev Log message Author Age Path
1765 root 5573d 08h /or1k/tags/nog_patch_37/or1ksim/cache/
1399 This commit was manufactured by cvs2svn to create tag 'nog_patch_37'. 7013d 16h /or1k/tags/nog_patch_37/or1ksim/cache/
1386 Rework exception handling nogj 7019d 19h /or1k/tags/nog_patch_37/or1ksim/cache/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7028d 19h /or1k/tags/nog_patch_37/or1ksim/cache/
1376 aclocal && autoconf && automake phoenix 7047d 19h /or1k/tags/nog_patch_37/or1ksim/cache/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7054d 10h /or1k/tags/nog_patch_37/or1ksim/cache/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7063d 14h /or1k/tags/nog_patch_37/or1ksim/cache/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7076d 17h /or1k/tags/nog_patch_37/or1ksim/cache/
1308 Gyorgy Jeney: extensive cleanup phoenix 7268d 08h /or1k/tags/nog_patch_37/or1ksim/cache/
1249 Downgrading back to automake-1.4 lampret 7433d 08h /or1k/tags/nog_patch_37/or1ksim/cache/
1117 Ignore generated files for CVS purposes sfurman 7776d 08h /or1k/tags/nog_patch_37/or1ksim/cache/
1099 cvs bug fixed markom 7862d 20h /or1k/tags/nog_patch_37/or1ksim/cache/
1085 Bug fixed. simons 7875d 10h /or1k/tags/nog_patch_37/or1ksim/cache/
997 PRINTF should be used instead of printf; command redirection repaired markom 7964d 23h /or1k/tags/nog_patch_37/or1ksim/cache/
992 A bug when cache enabled and bus error comes fixed. simons 7966d 14h /or1k/tags/nog_patch_37/or1ksim/cache/
970 Testbench is now running on ORP architecture platform. simons 7972d 10h /or1k/tags/nog_patch_37/or1ksim/cache/
884 code cleaning - a lot of global variables moved to runtime struct markom 8008d 21h /or1k/tags/nog_patch_37/or1ksim/cache/
876 Beta release of ATA simulation rherveille 8016d 09h /or1k/tags/nog_patch_37/or1ksim/cache/
638 TLBTR CI bit is now working properly. simons 8167d 10h /or1k/tags/nog_patch_37/or1ksim/cache/
631 Real cache access is simulated now. simons 8170d 09h /or1k/tags/nog_patch_37/or1ksim/cache/

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