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[/] [or1k/] [tags/] [nog_patch_38/] [or1ksim/] [cpu/] - Rev 1061

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Rev Log message Author Age Path
1061 ELF sym loading improved markom 7974d 23h /or1k/tags/nog_patch_38/or1ksim/cpu/
1049 Added "breaks" command that prints all set breakpoints. ivang 8001d 20h /or1k/tags/nog_patch_38/or1ksim/cpu/
1034 Fixed encoding for l.div/l.divu. lampret 8007d 10h /or1k/tags/nog_patch_38/or1ksim/cpu/
1025 PRINTF/printf mess fixed. simons 8010d 17h /or1k/tags/nog_patch_38/or1ksim/cpu/
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 8011d 01h /or1k/tags/nog_patch_38/or1ksim/cpu/
997 PRINTF should be used instead of printf; command redirection repaired markom 8023d 04h /or1k/tags/nog_patch_38/or1ksim/cpu/
992 A bug when cache enabled and bus error comes fixed. simons 8024d 20h /or1k/tags/nog_patch_38/or1ksim/cpu/
970 Testbench is now running on ORP architecture platform. simons 8030d 15h /or1k/tags/nog_patch_38/or1ksim/cpu/
914 SR[FO] is always set to 1. lampret 8047d 03h /or1k/tags/nog_patch_38/or1ksim/cpu/
913 Executed log insns counter output in decimal instead of hex. lampret 8047d 04h /or1k/tags/nog_patch_38/or1ksim/cpu/
911 Added instruction count to hardware executed log lampret 8047d 04h /or1k/tags/nog_patch_38/or1ksim/cpu/
897 improved CUC GUI; pre/unroll bugs fixed markom 8059d 20h /or1k/tags/nog_patch_38/or1ksim/cpu/
886 MMU registers reserved fields protected from writing. simons 8066d 20h /or1k/tags/nog_patch_38/or1ksim/cpu/
884 code cleaning - a lot of global variables moved to runtime struct markom 8067d 02h /or1k/tags/nog_patch_38/or1ksim/cpu/
883 cuc updated, cuc prompt parsing; CSM analysis markom 8067d 21h /or1k/tags/nog_patch_38/or1ksim/cpu/
882 Routine for adjusting read and write delay for devices added. simons 8070d 00h /or1k/tags/nog_patch_38/or1ksim/cpu/
879 Initial version of OpenRISC Custom Unit Compiler added markom 8072d 20h /or1k/tags/nog_patch_38/or1ksim/cpu/
877 ata beta release rherveille 8074d 14h /or1k/tags/nog_patch_38/or1ksim/cpu/
876 Beta release of ATA simulation rherveille 8074d 14h /or1k/tags/nog_patch_38/or1ksim/cpu/
860 Added delayr and delayw variable initialization (default value 1) ivang 8114d 14h /or1k/tags/nog_patch_38/or1ksim/cpu/

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