OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_42/] - Rev 358

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
358 Fixed virtual silicon single-port rams instantiation. lampret 8269d 12h /or1k/tags/nog_patch_42/
357 Fixed dbg_is_o assignment width. lampret 8269d 13h /or1k/tags/nog_patch_42/
356 Break point bug fixed simons 8269d 15h /or1k/tags/nog_patch_42/
355 uart VAPI model improved; changes to MC and eth. markom 8269d 22h /or1k/tags/nog_patch_42/
354 Fixed width of du_except. lampret 8270d 09h /or1k/tags/nog_patch_42/
353 Cashes disabled. simons 8270d 19h /or1k/tags/nog_patch_42/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8271d 22h /or1k/tags/nog_patch_42/
351 Fixed some l.trap typos. lampret 8272d 00h /or1k/tags/nog_patch_42/
350 For GDB changed single stepping and disabled trap exception. lampret 8272d 01h /or1k/tags/nog_patch_42/
349 Some bugs regarding cache simulation fixed. simons 8273d 14h /or1k/tags/nog_patch_42/
348 Added instructions on how to build configure. ivang 8274d 22h /or1k/tags/nog_patch_42/
347 Added CRC32 calculation to Ethernet erez 8275d 19h /or1k/tags/nog_patch_42/
346 Improved Ethernet simulation erez 8275d 20h /or1k/tags/nog_patch_42/
345 Added check for net/ethernet.h (needed by ethernet simulator) erez 8275d 20h /or1k/tags/nog_patch_42/
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8275d 22h /or1k/tags/nog_patch_42/
343 Small touches to test programs erez 8276d 01h /or1k/tags/nog_patch_42/
342 added exception vectors to support and modified section names markom 8276d 21h /or1k/tags/nog_patch_42/
341 added VAPI for uart; uart 16550 support, some bugs fixed markom 8276d 23h /or1k/tags/nog_patch_42/
340 Added hpint vector lampret 8277d 00h /or1k/tags/nog_patch_42/
339 Added setpc test lampret 8277d 00h /or1k/tags/nog_patch_42/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.