OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_46/] [or1ksim/] [cache/] - Rev 1779

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5599d 15h /or1k/tags/nog_patch_46/or1ksim/cache/
1417 This commit was manufactured by cvs2svn to create tag 'nog_patch_46'. 7039d 22h /or1k/tags/nog_patch_46/or1ksim/cache/
1406 Fix the declaration of `sec' in reg_ic_sec nogj 7039d 22h /or1k/tags/nog_patch_46/or1ksim/cache/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7039d 22h /or1k/tags/nog_patch_46/or1ksim/cache/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7039d 22h /or1k/tags/nog_patch_46/or1ksim/cache/
1386 Rework exception handling nogj 7046d 02h /or1k/tags/nog_patch_46/or1ksim/cache/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.
nogj 7055d 02h /or1k/tags/nog_patch_46/or1ksim/cache/
1376 aclocal && autoconf && automake phoenix 7074d 02h /or1k/tags/nog_patch_46/or1ksim/cache/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7080d 17h /or1k/tags/nog_patch_46/or1ksim/cache/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7089d 20h /or1k/tags/nog_patch_46/or1ksim/cache/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7103d 00h /or1k/tags/nog_patch_46/or1ksim/cache/
1308 Gyorgy Jeney: extensive cleanup phoenix 7294d 15h /or1k/tags/nog_patch_46/or1ksim/cache/
1249 Downgrading back to automake-1.4 lampret 7459d 15h /or1k/tags/nog_patch_46/or1ksim/cache/
1117 Ignore generated files for CVS purposes sfurman 7802d 15h /or1k/tags/nog_patch_46/or1ksim/cache/
1099 cvs bug fixed markom 7889d 02h /or1k/tags/nog_patch_46/or1ksim/cache/
1085 Bug fixed. simons 7901d 16h /or1k/tags/nog_patch_46/or1ksim/cache/
997 PRINTF should be used instead of printf; command redirection repaired markom 7991d 05h /or1k/tags/nog_patch_46/or1ksim/cache/
992 A bug when cache enabled and bus error comes fixed. simons 7992d 21h /or1k/tags/nog_patch_46/or1ksim/cache/
970 Testbench is now running on ORP architecture platform. simons 7998d 16h /or1k/tags/nog_patch_46/or1ksim/cache/
884 code cleaning - a lot of global variables moved to runtime struct markom 8035d 03h /or1k/tags/nog_patch_46/or1ksim/cache/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.