OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_48/] - Rev 992

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
992 A bug when cache enabled and bus error comes fixed. simons 7995d 04h /or1k/tags/nog_patch_48/
991 Different memory controller. simons 7995d 04h /or1k/tags/nog_patch_48/
990 Test is now complete. simons 7995d 04h /or1k/tags/nog_patch_48/
989 c++ is making problems so, for now, it is excluded. simons 7996d 12h /or1k/tags/nog_patch_48/
988 ORP architecture supported. simons 7997d 03h /or1k/tags/nog_patch_48/
987 ORP architecture supported. simons 7997d 11h /or1k/tags/nog_patch_48/
986 outputs out of function are not registered anymore markom 7997d 11h /or1k/tags/nog_patch_48/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7997d 23h /or1k/tags/nog_patch_48/
984 Disable SB until it is tested lampret 7997d 23h /or1k/tags/nog_patch_48/
983 First checkin lampret 7998d 01h /or1k/tags/nog_patch_48/
982 Moved to sim/bin lampret 7998d 01h /or1k/tags/nog_patch_48/
981 First checkin. lampret 7998d 01h /or1k/tags/nog_patch_48/
980 Removed sim.tcl that shouldn't be here. lampret 7998d 01h /or1k/tags/nog_patch_48/
979 Removed old test case binaries. lampret 7998d 01h /or1k/tags/nog_patch_48/
978 Added variable delay for SRAM. lampret 7998d 01h /or1k/tags/nog_patch_48/
977 Added store buffer. lampret 7998d 01h /or1k/tags/nog_patch_48/
976 Added store buffer lampret 7998d 01h /or1k/tags/nog_patch_48/
975 First checkin lampret 7998d 01h /or1k/tags/nog_patch_48/
974 Enabled what works on or1ksim and disabled other tests. lampret 7998d 03h /or1k/tags/nog_patch_48/
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8000d 07h /or1k/tags/nog_patch_48/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.