OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_49/] - Rev 198

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
198 Moved from testbench.old simons 8345d 21h /or1k/tags/nog_patch_49/
197 This is not used any more. simons 8345d 21h /or1k/tags/nog_patch_49/
196 Configuration SPRs added. simons 8345d 21h /or1k/tags/nog_patch_49/
195 New test added. simons 8345d 21h /or1k/tags/nog_patch_49/
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.
chris 8346d 05h /or1k/tags/nog_patch_49/
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.
chris 8346d 05h /or1k/tags/nog_patch_49/
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.
chris 8346d 14h /or1k/tags/nog_patch_49/
191 Added UART jitter var to sim config chris 8347d 11h /or1k/tags/nog_patch_49/
190 Added jitter initialization chris 8347d 11h /or1k/tags/nog_patch_49/
189 fixed mode handling for tick facility chris 8347d 11h /or1k/tags/nog_patch_49/
188 fixed PIC interrupt controller chris 8347d 11h /or1k/tags/nog_patch_49/
187 minor change to clear pending exception chris 8347d 11h /or1k/tags/nog_patch_49/
186 major change to UART structure chris 8347d 11h /or1k/tags/nog_patch_49/
185 major change to UART code chris 8347d 11h /or1k/tags/nog_patch_49/
184 modified decode for trace debugging chris 8347d 11h /or1k/tags/nog_patch_49/
183 changed special case for PICSR chris 8347d 11h /or1k/tags/nog_patch_49/
182 updated exception handling procedures chris 8347d 11h /or1k/tags/nog_patch_49/
181 Added trace/stall commands chris 8347d 11h /or1k/tags/nog_patch_49/
180 Updated debug. lampret 8347d 17h /or1k/tags/nog_patch_49/
179 Sim run script lampret 8367d 09h /or1k/tags/nog_patch_49/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.