OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_49/] - Rev 994

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8027d 13h /or1k/tags/nog_patch_49/
993 Fixed IMMU bug. lampret 8027d 13h /or1k/tags/nog_patch_49/
992 A bug when cache enabled and bus error comes fixed. simons 8027d 22h /or1k/tags/nog_patch_49/
991 Different memory controller. simons 8027d 22h /or1k/tags/nog_patch_49/
990 Test is now complete. simons 8027d 22h /or1k/tags/nog_patch_49/
989 c++ is making problems so, for now, it is excluded. simons 8029d 06h /or1k/tags/nog_patch_49/
988 ORP architecture supported. simons 8029d 21h /or1k/tags/nog_patch_49/
987 ORP architecture supported. simons 8030d 05h /or1k/tags/nog_patch_49/
986 outputs out of function are not registered anymore markom 8030d 05h /or1k/tags/nog_patch_49/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8030d 17h /or1k/tags/nog_patch_49/
984 Disable SB until it is tested lampret 8030d 17h /or1k/tags/nog_patch_49/
983 First checkin lampret 8030d 19h /or1k/tags/nog_patch_49/
982 Moved to sim/bin lampret 8030d 19h /or1k/tags/nog_patch_49/
981 First checkin. lampret 8030d 19h /or1k/tags/nog_patch_49/
980 Removed sim.tcl that shouldn't be here. lampret 8030d 19h /or1k/tags/nog_patch_49/
979 Removed old test case binaries. lampret 8030d 19h /or1k/tags/nog_patch_49/
978 Added variable delay for SRAM. lampret 8030d 19h /or1k/tags/nog_patch_49/
977 Added store buffer. lampret 8030d 19h /or1k/tags/nog_patch_49/
976 Added store buffer lampret 8030d 19h /or1k/tags/nog_patch_49/
975 First checkin lampret 8030d 19h /or1k/tags/nog_patch_49/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.