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[/] [or1k/] [tags/] [nog_patch_52/] - Rev 994

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Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8016d 03h /or1k/tags/nog_patch_52/
993 Fixed IMMU bug. lampret 8016d 03h /or1k/tags/nog_patch_52/
992 A bug when cache enabled and bus error comes fixed. simons 8016d 12h /or1k/tags/nog_patch_52/
991 Different memory controller. simons 8016d 12h /or1k/tags/nog_patch_52/
990 Test is now complete. simons 8016d 12h /or1k/tags/nog_patch_52/
989 c++ is making problems so, for now, it is excluded. simons 8017d 20h /or1k/tags/nog_patch_52/
988 ORP architecture supported. simons 8018d 12h /or1k/tags/nog_patch_52/
987 ORP architecture supported. simons 8018d 19h /or1k/tags/nog_patch_52/
986 outputs out of function are not registered anymore markom 8018d 20h /or1k/tags/nog_patch_52/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8019d 07h /or1k/tags/nog_patch_52/
984 Disable SB until it is tested lampret 8019d 07h /or1k/tags/nog_patch_52/
983 First checkin lampret 8019d 09h /or1k/tags/nog_patch_52/
982 Moved to sim/bin lampret 8019d 09h /or1k/tags/nog_patch_52/
981 First checkin. lampret 8019d 09h /or1k/tags/nog_patch_52/
980 Removed sim.tcl that shouldn't be here. lampret 8019d 10h /or1k/tags/nog_patch_52/
979 Removed old test case binaries. lampret 8019d 10h /or1k/tags/nog_patch_52/
978 Added variable delay for SRAM. lampret 8019d 10h /or1k/tags/nog_patch_52/
977 Added store buffer. lampret 8019d 10h /or1k/tags/nog_patch_52/
976 Added store buffer lampret 8019d 10h /or1k/tags/nog_patch_52/
975 First checkin lampret 8019d 10h /or1k/tags/nog_patch_52/

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