OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] - Rev 998

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
998 added missing fout initialization markom 8048d 00h /or1k/tags/nog_patch_61/
997 PRINTF should be used instead of printf; command redirection repaired markom 8048d 01h /or1k/tags/nog_patch_61/
996 some minor bugs fixed markom 8048d 23h /or1k/tags/nog_patch_61/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8049d 07h /or1k/tags/nog_patch_61/
993 Fixed IMMU bug. lampret 8049d 07h /or1k/tags/nog_patch_61/
992 A bug when cache enabled and bus error comes fixed. simons 8049d 16h /or1k/tags/nog_patch_61/
991 Different memory controller. simons 8049d 16h /or1k/tags/nog_patch_61/
990 Test is now complete. simons 8049d 16h /or1k/tags/nog_patch_61/
989 c++ is making problems so, for now, it is excluded. simons 8051d 00h /or1k/tags/nog_patch_61/
988 ORP architecture supported. simons 8051d 16h /or1k/tags/nog_patch_61/
987 ORP architecture supported. simons 8051d 23h /or1k/tags/nog_patch_61/
986 outputs out of function are not registered anymore markom 8052d 00h /or1k/tags/nog_patch_61/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8052d 11h /or1k/tags/nog_patch_61/
984 Disable SB until it is tested lampret 8052d 11h /or1k/tags/nog_patch_61/
983 First checkin lampret 8052d 13h /or1k/tags/nog_patch_61/
982 Moved to sim/bin lampret 8052d 13h /or1k/tags/nog_patch_61/
981 First checkin. lampret 8052d 13h /or1k/tags/nog_patch_61/
980 Removed sim.tcl that shouldn't be here. lampret 8052d 13h /or1k/tags/nog_patch_61/
979 Removed old test case binaries. lampret 8052d 13h /or1k/tags/nog_patch_61/
978 Added variable delay for SRAM. lampret 8052d 13h /or1k/tags/nog_patch_61/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.