OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_67/] [gen_or1k_isa/] [sources/] [opcode/] - Rev 1765

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5563d 21h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1460 This commit was manufactured by cvs2svn to create tag 'nog_patch_67'. 7004d 04h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1452 Implement a dynamic recompiler to speed up the execution nogj 7004d 04h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1440 Reclasify l.trap and l.sys to be an exception instruction nogj 7004d 04h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 7019d 08h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7054d 02h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1346 Remove the global op structure nogj 7067d 06h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
nogj 7067d 06h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7067d 07h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1338 l.ff1 instruction added andreje 7083d 04h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1309 removed includes phoenix 7256d 00h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1308 Gyorgy Jeney: extensive cleanup phoenix 7258d 21h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7280d 21h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1286 Changed desciption of the l.cust5 insns lampret 7330d 00h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1285 Changed desciption of the l.cust5 insns lampret 7330d 00h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1169 Added support for l.addc instruction. csanchez 7643d 00h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1114 Added cvs log keywords lampret 7797d 16h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
1034 Fixed encoding for l.div/l.divu. lampret 7939d 18h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
879 Initial version of OpenRISC Custom Unit Compiler added markom 8005d 03h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/
801 l.muli instruction added markom 8097d 07h /or1k/tags/nog_patch_67/gen_or1k_isa/sources/opcode/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.