OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_72/] - Rev 171

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
171 Added monitor.v and timescale.v lampret 8393d 12h /or1k/tags/nog_patch_72/
170 Added cfg regs. Moved all defines into one defines.v file. More cleanup. lampret 8393d 12h /or1k/tags/nog_patch_72/
169 Fixed memory cells. Moved monitor.h into monitor.v lampret 8393d 12h /or1k/tags/nog_patch_72/
168 Major clean-up. lampret 8397d 02h /or1k/tags/nog_patch_72/
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed
markom 8398d 02h /or1k/tags/nog_patch_72/
166 Fixed RAM's oen bug. Cache bypass under development. lampret 8415d 13h /or1k/tags/nog_patch_72/
165 Added variable ack of WB transfers (see NODELAY_WBx). lampret 8415d 13h /or1k/tags/nog_patch_72/
164 *** empty log message *** lampret 8417d 15h /or1k/tags/nog_patch_72/
163 Forgot files.f file. lampret 8417d 15h /or1k/tags/nog_patch_72/
162 Benches (under development). lampret 8417d 15h /or1k/tags/nog_patch_72/
161 Development version of RTL. Libraries are missing. lampret 8417d 15h /or1k/tags/nog_patch_72/
160 simulation script lampret 8417d 15h /or1k/tags/nog_patch_72/
159 synthesis scripts lampret 8417d 15h /or1k/tags/nog_patch_72/
158 Initial RTEMS import chris 8427d 06h /or1k/tags/nog_patch_72/
157 Update simons 8434d 09h /or1k/tags/nog_patch_72/
156 File moved to opcode. simons 8434d 09h /or1k/tags/nog_patch_72/
155 Update simons 8434d 09h /or1k/tags/nog_patch_72/
154 Updated for new runtime environment chris 8440d 09h /or1k/tags/nog_patch_72/
153 Writes to SPR_PC are now enabled chris 8440d 09h /or1k/tags/nog_patch_72/
152 Breakpoint exceptions from single step are not printed now. chris 8440d 09h /or1k/tags/nog_patch_72/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.