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[/] [or1k/] [tags/] [nog_patch_72/] [or1ksim/] [cpu/] [or1k/] - Rev 1765

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1765 root 5586d 16h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1470 This commit was manufactured by cvs2svn to create tag 'nog_patch_72'. 7026d 22h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1452 Implement a dynamic recompiler to speed up the execution nogj 7026d 22h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1446 Cosmetic fixes nogj 7026d 22h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1444 Move the definitions needed for the simple execution model out of or32.h and into simpl32_defs.h nogj 7026d 22h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1442 Replace some problematic calles to mfspr/mtspr with direct access to the spr nogj 7026d 22h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7026d 22h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7026d 23h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7026d 23h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1386 Rework exception handling nogj 7033d 02h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7042d 02h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1376 aclocal && autoconf && automake phoenix 7061d 02h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1354 typing fixes phoenix 7076d 00h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7076d 21h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7090d 01h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.		 nogj 7090d 01h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7090d 01h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1338 l.ff1 instruction added andreje 7105d 23h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7193d 16h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/
1316 added a warning phoenix 7211d 13h /or1k/tags/nog_patch_72/or1ksim/cpu/or1k/

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