OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] - Rev 1204

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1204 added additional field into executed log wich besides EA also prints PA (physical address) phoenix 7578d 10h /or1k/tags/rel-0-3-0-rc2/
1203 value stored in ITLB and DTLB match registers was wrong. fixed. phoenix 7578d 10h /or1k/tags/rel-0-3-0-rc2/
1202 at exception print insn number to ease debugging phoenix 7578d 11h /or1k/tags/rel-0-3-0-rc2/
1200 mbist signals updated according to newest convention markom 7603d 06h /or1k/tags/rel-0-3-0-rc2/
1199 Daniel Wiklund: Removed multiple entries of debug/Makefile in configure danwi 7607d 07h /or1k/tags/rel-0-3-0-rc2/
1198 make it compile on RH 8,9 phoenix 7632d 21h /or1k/tags/rel-0-3-0-rc2/
1197 disabled ram-init of ps2 (old) +
changed MAC type into DOS type, so that Xilinx ISE can work with it
dries 7638d 02h /or1k/tags/rel-0-3-0-rc2/
1196 removed second debug/Makefile (credits: Daniel Wiklund - danwi@isy.liu.se) dries 7638d 04h /or1k/tags/rel-0-3-0-rc2/
1195 made the project file a little bit more universal dries 7638d 05h /or1k/tags/rel-0-3-0-rc2/
1194 correct all the syntax errors dries 7638d 05h /or1k/tags/rel-0-3-0-rc2/
1193 disabled SRAM_GENERIC and added comment +
corrected 'wb_err' into 'wb_err_o'
dries 7638d 05h /or1k/tags/rel-0-3-0-rc2/
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7638d 07h /or1k/tags/rel-0-3-0-rc2/
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7638d 07h /or1k/tags/rel-0-3-0-rc2/
1188 Added support for rams with byte write access. simons 7654d 05h /or1k/tags/rel-0-3-0-rc2/
1186 Added support for rams with byte write access. simons 7655d 04h /or1k/tags/rel-0-3-0-rc2/
1184 Scan signals mess fixed. simons 7661d 21h /or1k/tags/rel-0-3-0-rc2/
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7666d 13h /or1k/tags/rel-0-3-0-rc2/
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7666d 15h /or1k/tags/rel-0-3-0-rc2/
1179 BIST interface added for Artisan memory instances. simons 7670d 00h /or1k/tags/rel-0-3-0-rc2/
1178 avoid another immu exception that should not happen phoenix 7699d 12h /or1k/tags/rel-0-3-0-rc2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.