OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] - Rev 201

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8341d 04h /or1k/tags/rel-0-3-0-rc2/
200 Initial import simons 8344d 11h /or1k/tags/rel-0-3-0-rc2/
199 Initial import simons 8344d 13h /or1k/tags/rel-0-3-0-rc2/
198 Moved from testbench.old simons 8347d 00h /or1k/tags/rel-0-3-0-rc2/
197 This is not used any more. simons 8347d 00h /or1k/tags/rel-0-3-0-rc2/
196 Configuration SPRs added. simons 8347d 00h /or1k/tags/rel-0-3-0-rc2/
195 New test added. simons 8347d 00h /or1k/tags/rel-0-3-0-rc2/
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8347d 08h /or1k/tags/rel-0-3-0-rc2/
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8347d 08h /or1k/tags/rel-0-3-0-rc2/
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8347d 17h /or1k/tags/rel-0-3-0-rc2/
191 Added UART jitter var to sim config chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
190 Added jitter initialization chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
189 fixed mode handling for tick facility chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
188 fixed PIC interrupt controller chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
187 minor change to clear pending exception chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
186 major change to UART structure chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
185 major change to UART code chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
184 modified decode for trace debugging chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
183 changed special case for PICSR chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/
182 updated exception handling procedures chris 8348d 14h /or1k/tags/rel-0-3-0-rc2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.