OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] - Rev 1545

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1545 move sched_next_insn from sim-cmd.c to sched.c. It is also usefull for the pic and the tick timer nogj 6922d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1544 Print the exit code in decimal, like with the complex execution nogj 6922d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1543 Try to find a symbolic name of the location where we crashed nogj 6922d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1542 Print stackdump to stderr instead of stdout nogj 6922d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1541 Print the scheduler jobs when the sched_jobs debug channel has been specified nogj 6922d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1540 * Breakup the tick_job function into smaller ones.
* Fix lots of conner cases.
* Add tests for the tick timer.
nogj 6922d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1539 Speed up the dmmu nogj 6923d 06h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1538 Speed up the immu nogj 6923d 06h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1537 Remove old spr logging code. Use `-d +spr' to get spr access logged to stderr nogj 6923d 06h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1532 Add pretty spr dumping code nogj 6926d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1531 Remove non-trigerable out-of-range checks nogj 6926d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1530 Move the checking of the debug channel into the TRACE() macro nogj 6926d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1529 * The effective address as written to the I/DCBPR registers needs to be translated by the respective mmu.
* Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR, ICBPR and ICBIR.
nogj 6927d 19h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1528 s/HAS_ISBLANK/HAVE_ISBLANK/ fix compileing on windows/cygwin. Reported by Kuoping Hsu and Girish Venkatar nogj 6928d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1527 Fix the execution log when an mtspr instruction causes an itlb miss nogj 6928d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1526 Fix a very outdated comment nogj 6928d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1525 Rename ADDR_PAGE to IADDR_PAGE nogj 6928d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1524 Check OR32_IF_DELAY instead of it_jump || it_branch nogj 6928d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1523 Bring config files up-to-date with recent changes nogj 6928d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/
1522 Add the cycles debug channel to print the value of the cycle counter before each line nogj 6928d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.