OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [cpu/] - Rev 133

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
133 moved header files to match other utilities
repaired l.sra and some other shifting instructions
started build_automata for binary instruction decode
markom 8489d 15h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
129 Added code to inject insn from Debug Unit DIR chris 8490d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
128 Added code to check debug unit after an exception chris 8490d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
123 Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault

Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files
markom 8496d 12h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8521d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
99 *** empty log message *** lampret 8536d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
98 Return value register is now r9. lampret 8536d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
90 Added tick timer. lampret 8567d 04h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
83 Updates. lampret 8568d 12h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
82 Changed pctemp to pcnext. lampret 8568d 12h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
77 Regular update. lampret 8721d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8740d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
67 Added simulator "application load". lampret 8740d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.
lampret 8740d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
65 Added DMMU stats. lampret 8740d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
64 SPR bit definition moved to spr_defs.h. lampret 8740d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).
lampret 8740d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
54 Regular maintenance. lampret 8791d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
52 Comment character changed. lampret 8852d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
51 Exception detection changed a bit. lampret 8852d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.