OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [pm/] - Rev 1745

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1745 These are the changes to allow or1ksim to build as a library as well as a standalone simulator. The concept of a "generic" peripheral is added, which will commuicate with an external model via upcalls. jeremybennett 5791d 21h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1744 Changes to bring behavior into line with the current OpenRISC 1000 specification and support GDB 6.8. A couple of small bugs with handling xterms and opening the remote debug channel are also fixed. Header files have been added to sources in Makefile.am files where they are missing, so that "make tags" will include them. Makefile.in files have been regenerated due to these changes. jeremybennett 5792d 21h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1649 Mark as many functions as possible static nogj 6752d 20h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1576 configure updates phoenix 6865d 16h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1508 Remove m{f,t}spr calls where we can access the spr directly nogj 6956d 04h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7046d 23h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1376 aclocal && autoconf && automake phoenix 7081d 03h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7087d 18h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7096d 22h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1249 Downgrading back to automake-1.4 lampret 7466d 16h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
1117 Ignore generated files for CVS purposes sfurman 7809d 16h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
997 PRINTF should be used instead of printf; command redirection repaired markom 7998d 07h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
970 Testbench is now running on ORP architecture platform. simons 8005d 18h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
876 Beta release of ATA simulation rherveille 8049d 17h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
805 kbd, fb, vga devices now uses scheduler markom 8133d 08h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
517 some performance optimizations markom 8229d 01h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
500 Added .cvsignore files for annoying generated files erez 8231d 05h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8301d 04h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed
markom 8378d 01h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8460d 10h /or1k/tags/rel-0-3-0-rc3/or1ksim/pm/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.