OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] - Rev 1779

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5562d 08h /or1k/tags/rel_1/or1200/
896 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7993d 09h /or1k/tags/rel_1/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 7993d 09h /or1k/tags/rel_1/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8029d 14h /or1k/tags/rel_1/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8029d 14h /or1k/tags/rel_1/or1200/
869 Added generic flip-flop based memory macro instantiation. lampret 8029d 15h /or1k/tags/rel_1/or1200/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8100d 14h /or1k/tags/rel_1/or1200/
794 Added again just recently removed full_case directive lampret 8100d 14h /or1k/tags/rel_1/or1200/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8100d 14h /or1k/tags/rel_1/or1200/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8100d 14h /or1k/tags/rel_1/or1200/
788 Some of the warnings fixed. lampret 8100d 16h /or1k/tags/rel_1/or1200/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8101d 11h /or1k/tags/rel_1/or1200/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8101d 12h /or1k/tags/rel_1/or1200/
776 Updated defines. lampret 8101d 12h /or1k/tags/rel_1/or1200/
775 Optimized cache controller FSM. lampret 8101d 12h /or1k/tags/rel_1/or1200/
774 Removed old files. lampret 8101d 12h /or1k/tags/rel_1/or1200/
737 Added alternative for critical path in DU. lampret 8116d 06h /or1k/tags/rel_1/or1200/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8119d 05h /or1k/tags/rel_1/or1200/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8119d 05h /or1k/tags/rel_1/or1200/
668 Lapsus fixed. simons 8143d 15h /or1k/tags/rel_1/or1200/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.