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[/] [or1k/] [tags/] [rel_10/] - Rev 993

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Rev Log message Author Age Path
993 Fixed IMMU bug. lampret 8013d 21h /or1k/tags/rel_10/
992 A bug when cache enabled and bus error comes fixed. simons 8014d 06h /or1k/tags/rel_10/
991 Different memory controller. simons 8014d 06h /or1k/tags/rel_10/
990 Test is now complete. simons 8014d 06h /or1k/tags/rel_10/
989 c++ is making problems so, for now, it is excluded. simons 8015d 14h /or1k/tags/rel_10/
988 ORP architecture supported. simons 8016d 06h /or1k/tags/rel_10/
987 ORP architecture supported. simons 8016d 13h /or1k/tags/rel_10/
986 outputs out of function are not registered anymore markom 8016d 14h /or1k/tags/rel_10/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8017d 01h /or1k/tags/rel_10/
984 Disable SB until it is tested lampret 8017d 01h /or1k/tags/rel_10/
983 First checkin lampret 8017d 03h /or1k/tags/rel_10/
982 Moved to sim/bin lampret 8017d 03h /or1k/tags/rel_10/
981 First checkin. lampret 8017d 03h /or1k/tags/rel_10/
980 Removed sim.tcl that shouldn't be here. lampret 8017d 03h /or1k/tags/rel_10/
979 Removed old test case binaries. lampret 8017d 03h /or1k/tags/rel_10/
978 Added variable delay for SRAM. lampret 8017d 03h /or1k/tags/rel_10/
977 Added store buffer. lampret 8017d 04h /or1k/tags/rel_10/
976 Added store buffer lampret 8017d 04h /or1k/tags/rel_10/
975 First checkin lampret 8017d 04h /or1k/tags/rel_10/
974 Enabled what works on or1ksim and disabled other tests. lampret 8017d 06h /or1k/tags/rel_10/

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