OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_10/] [or1200/] - Rev 1022

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7986d 10h /or1k/tags/rel_10/or1200/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7993d 07h /or1k/tags/rel_10/or1200/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7999d 07h /or1k/tags/rel_10/or1200/
993 Fixed IMMU bug. lampret 7999d 07h /or1k/tags/rel_10/or1200/
984 Disable SB until it is tested lampret 8002d 11h /or1k/tags/rel_10/or1200/
977 Added store buffer. lampret 8002d 13h /or1k/tags/rel_10/or1200/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8006d 03h /or1k/tags/rel_10/or1200/
960 Directory cleanup. lampret 8006d 03h /or1k/tags/rel_10/or1200/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8007d 03h /or1k/tags/rel_10/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8009d 03h /or1k/tags/rel_10/or1200/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8009d 03h /or1k/tags/rel_10/or1200/
942 Delayed external access at page crossing. lampret 8009d 03h /or1k/tags/rel_10/or1200/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8021d 07h /or1k/tags/rel_10/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8037d 11h /or1k/tags/rel_10/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8073d 17h /or1k/tags/rel_10/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8073d 17h /or1k/tags/rel_10/or1200/
869 Added generic flip-flop based memory macro instantiation. lampret 8073d 17h /or1k/tags/rel_10/or1200/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8144d 16h /or1k/tags/rel_10/or1200/
794 Added again just recently removed full_case directive lampret 8144d 16h /or1k/tags/rel_10/or1200/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8144d 16h /or1k/tags/rel_10/or1200/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.