OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_10/] [or1200/] - Rev 958

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7991d 03h /or1k/tags/rel_10/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7993d 03h /or1k/tags/rel_10/or1200/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 7993d 03h /or1k/tags/rel_10/or1200/
942 Delayed external access at page crossing. lampret 7993d 04h /or1k/tags/rel_10/or1200/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8005d 07h /or1k/tags/rel_10/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8021d 11h /or1k/tags/rel_10/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8057d 17h /or1k/tags/rel_10/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8057d 17h /or1k/tags/rel_10/or1200/
869 Added generic flip-flop based memory macro instantiation. lampret 8057d 17h /or1k/tags/rel_10/or1200/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8128d 16h /or1k/tags/rel_10/or1200/
794 Added again just recently removed full_case directive lampret 8128d 16h /or1k/tags/rel_10/or1200/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8128d 17h /or1k/tags/rel_10/or1200/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8128d 17h /or1k/tags/rel_10/or1200/
788 Some of the warnings fixed. lampret 8128d 18h /or1k/tags/rel_10/or1200/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8129d 14h /or1k/tags/rel_10/or1200/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8129d 14h /or1k/tags/rel_10/or1200/
776 Updated defines. lampret 8129d 14h /or1k/tags/rel_10/or1200/
775 Optimized cache controller FSM. lampret 8129d 14h /or1k/tags/rel_10/or1200/
774 Removed old files. lampret 8129d 14h /or1k/tags/rel_10/or1200/
737 Added alternative for critical path in DU. lampret 8144d 09h /or1k/tags/rel_10/or1200/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.