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[/] [or1k/] [tags/] [rel_12/] - Rev 1153

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1153 When multiple interrupts were pending, e.g. TX buffer empty and RX
available, reading the UART's IIR register could potentially clear a
TX interrupt before it had been sent to the processor, thus dropping
the interrupt permanently.

Fix tested w/ both eCos and uclinux.		 sfurman 7721d 07h /or1k/tags/rel_12/
1152 *** empty log message *** phoenix 7721d 11h /or1k/tags/rel_12/
1151 *** empty log message *** phoenix 7721d 11h /or1k/tags/rel_12/
1150 remove unneded include phoenix 7721d 13h /or1k/tags/rel_12/
1149 *** empty log message *** phoenix 7722d 00h /or1k/tags/rel_12/
1148 *** empty log message *** phoenix 7722d 01h /or1k/tags/rel_12/
1147 remove unneeded include phoenix 7722d 01h /or1k/tags/rel_12/
1146 cygwin fix phoenix 7722d 01h /or1k/tags/rel_12/
1145 1) Fix trivial bug w/ transmitter empty interrupts that I introduced in the
last check-in.
2) Improve printed output from debugging-only uart_status() routine.		 sfurman 7722d 01h /or1k/tags/rel_12/
1144 Speed up gdb when running with serial targets:

When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)

When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump.		 sfurman 7724d 07h /or1k/tags/rel_12/
1143 Make UART transmitter-empty interrupts match both 16450 and 16550 behavior. sfurman 7724d 22h /or1k/tags/rel_12/
1142 Speed up gdb when running with serial targets:

When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)

When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump.		 sfurman 7724d 22h /or1k/tags/rel_12/
1141 WB = 1/2 RISC clock test code enabled. lampret 7726d 07h /or1k/tags/rel_12/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7726d 07h /or1k/tags/rel_12/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7726d 07h /or1k/tags/rel_12/
1138 Added some information how to run simulations. lampret 7727d 02h /or1k/tags/rel_12/
1137 Added RFRAM generic and Altera lpm library. lampret 7727d 02h /or1k/tags/rel_12/
1136 Add altera lpm library. lampret 7727d 02h /or1k/tags/rel_12/
1135 Added get_gpr support for OR1200_RFRAM_GENERIC lampret 7727d 02h /or1k/tags/rel_12/
1134 Changed location of debug test code to 0. lampret 7727d 02h /or1k/tags/rel_12/

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