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[/] [or1k/] [tags/] [rel_12/] - Rev 206

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Rev Log message Author Age Path
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.		 chris 8326d 13h /or1k/tags/rel_12/
205 Adding debug capabilities. Half done. lampret 8330d 16h /or1k/tags/rel_12/
204 Added function prototypes to stop gcc from complaining erez 8333d 08h /or1k/tags/rel_12/
203 Updated from xess branch. lampret 8334d 21h /or1k/tags/rel_12/
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf		 erez 8340d 05h /or1k/tags/rel_12/
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8340d 05h /or1k/tags/rel_12/
200 Initial import simons 8343d 12h /or1k/tags/rel_12/
199 Initial import simons 8343d 13h /or1k/tags/rel_12/
198 Moved from testbench.old simons 8346d 00h /or1k/tags/rel_12/
197 This is not used any more. simons 8346d 00h /or1k/tags/rel_12/
196 Configuration SPRs added. simons 8346d 01h /or1k/tags/rel_12/
195 New test added. simons 8346d 01h /or1k/tags/rel_12/
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8346d 09h /or1k/tags/rel_12/
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8346d 09h /or1k/tags/rel_12/
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8346d 18h /or1k/tags/rel_12/
191 Added UART jitter var to sim config chris 8347d 15h /or1k/tags/rel_12/
190 Added jitter initialization chris 8347d 15h /or1k/tags/rel_12/
189 fixed mode handling for tick facility chris 8347d 15h /or1k/tags/rel_12/
188 fixed PIC interrupt controller chris 8347d 15h /or1k/tags/rel_12/
187 minor change to clear pending exception chris 8347d 15h /or1k/tags/rel_12/

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