URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_12/] - Rev 638

Rev	Log message	Author	Age	Path
638	TLBTR CI bit is now working properly.	simons	8199d 13h	/or1k/tags/rel_12/
637	Updated file names.	lampret	8199d 14h	/or1k/tags/rel_12/
636	Fixed combinational loops.	lampret	8199d 14h	/or1k/tags/rel_12/
635	Fixed Makefile bug.	ivang	8199d 16h	/or1k/tags/rel_12/
634	configure.in : fixed to build start/Makefile start.S : l.jalr r9 -> l.jr r9 Added missing files.	ivang	8200d 17h	/or1k/tags/rel_12/
633	Bug fix in command line parser.	ivang	8200d 18h	/or1k/tags/rel_12/
632	profiler and mprofiler merged into sim.	ivang	8201d 13h	/or1k/tags/rel_12/
631	Real cache access is simulated now.	simons	8202d 12h	/or1k/tags/rel_12/
630	some bug fixes in store buffer analysis	markom	8202d 21h	/or1k/tags/rel_12/
629	typo fixed	markom	8203d 00h	/or1k/tags/rel_12/
627	or32 restored	markom	8203d 01h	/or1k/tags/rel_12/
626	store buffer added	markom	8203d 01h	/or1k/tags/rel_12/
625	Bus error bug fixed. Cache routines added.	simons	8203d 17h	/or1k/tags/rel_12/
624	Added logging of writes/read to/from SPR registers.	ivang	8203d 18h	/or1k/tags/rel_12/
623	update based on recent changes; arithmetic instructions does not modify carry yet	markom	8203d 20h	/or1k/tags/rel_12/
622	Cache test works on hardware.	simons	8203d 23h	/or1k/tags/rel_12/
621	Cache test works on hardware.	simons	8204d 00h	/or1k/tags/rel_12/
620	use ARITH_SET_FLAG to turn off set flag by arith. instructions	markom	8204d 00h	/or1k/tags/rel_12/
619	all test pass, after newest changes	markom	8204d 00h	/or1k/tags/rel_12/
618	Fixed display of new 'void' nop insns.	lampret	8204d 09h	/or1k/tags/rel_12/