OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_12/] - Rev 803

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
803 Free irq handler fixed. simons 8135d 23h /or1k/tags/rel_12/
802 Cache and tick timer tests fixed. simons 8137d 10h /or1k/tags/rel_12/
801 l.muli instruction added markom 8139d 06h /or1k/tags/rel_12/
800 Bug fixed. simons 8140d 04h /or1k/tags/rel_12/
799 Wrapping around 512k boundary to simulate real hw. simons 8143d 21h /or1k/tags/rel_12/
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8143d 21h /or1k/tags/rel_12/
797 Changed hardcoded address for fake MC to use a define. lampret 8143d 23h /or1k/tags/rel_12/
796 Removed unused ports wb_clki and wb_rst_i lampret 8143d 23h /or1k/tags/rel_12/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8144d 03h /or1k/tags/rel_12/
794 Added again just recently removed full_case directive lampret 8144d 03h /or1k/tags/rel_12/
793 Added synthesis off/on for timescale.v included file. lampret 8144d 03h /or1k/tags/rel_12/
792 Fixed port names that changed. lampret 8144d 03h /or1k/tags/rel_12/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8144d 03h /or1k/tags/rel_12/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8144d 03h /or1k/tags/rel_12/
789 Added response from memory controller (addr 0x60000000) lampret 8144d 04h /or1k/tags/rel_12/
788 Some of the warnings fixed. lampret 8144d 04h /or1k/tags/rel_12/
787 Added romfs.tgz lampret 8144d 22h /or1k/tags/rel_12/
786 Moved UCF constraint file to the backend directory. lampret 8144d 23h /or1k/tags/rel_12/
785 Added XSV specific documentation. lampret 8144d 23h /or1k/tags/rel_12/
784 Added soem missing files. lampret 8144d 23h /or1k/tags/rel_12/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.