OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_12/] - Rev 999

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
999 Now every ramdisk image should have init program. simons 8027d 02h /or1k/tags/rel_12/
998 added missing fout initialization markom 8027d 04h /or1k/tags/rel_12/
997 PRINTF should be used instead of printf; command redirection repaired markom 8027d 05h /or1k/tags/rel_12/
996 some minor bugs fixed markom 8028d 04h /or1k/tags/rel_12/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8028d 11h /or1k/tags/rel_12/
993 Fixed IMMU bug. lampret 8028d 11h /or1k/tags/rel_12/
992 A bug when cache enabled and bus error comes fixed. simons 8028d 20h /or1k/tags/rel_12/
991 Different memory controller. simons 8028d 20h /or1k/tags/rel_12/
990 Test is now complete. simons 8028d 21h /or1k/tags/rel_12/
989 c++ is making problems so, for now, it is excluded. simons 8030d 04h /or1k/tags/rel_12/
988 ORP architecture supported. simons 8030d 20h /or1k/tags/rel_12/
987 ORP architecture supported. simons 8031d 03h /or1k/tags/rel_12/
986 outputs out of function are not registered anymore markom 8031d 04h /or1k/tags/rel_12/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8031d 15h /or1k/tags/rel_12/
984 Disable SB until it is tested lampret 8031d 16h /or1k/tags/rel_12/
983 First checkin lampret 8031d 18h /or1k/tags/rel_12/
982 Moved to sim/bin lampret 8031d 18h /or1k/tags/rel_12/
981 First checkin. lampret 8031d 18h /or1k/tags/rel_12/
980 Removed sim.tcl that shouldn't be here. lampret 8031d 18h /or1k/tags/rel_12/
979 Removed old test case binaries. lampret 8031d 18h /or1k/tags/rel_12/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.