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[/] [or1k/] [tags/] [rel_13/] - Rev 1023

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Rev Log message Author Age Path
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7981d 14h /or1k/tags/rel_13/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7981d 17h /or1k/tags/rel_13/
1021 *** empty log message *** rherveille 7985d 19h /or1k/tags/rel_13/
1020 Fixed several bugs
Working version, tested on Bender hardware		 rherveille 7985d 19h /or1k/tags/rel_13/
1019 fixed some bugs detected by Bender hardware rherveille 7985d 19h /or1k/tags/rel_13/
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 7986d 02h /or1k/tags/rel_13/
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 7986d 03h /or1k/tags/rel_13/
1016 64 bytes is the smallest packet size. simons 7986d 19h /or1k/tags/rel_13/
1015 Host type was not recognized. simons 7987d 05h /or1k/tags/rel_13/
1014 added _JBLEN definition for or1k ivang 7987d 18h /or1k/tags/rel_13/
1013 ORP architecture supported. simons 7987d 20h /or1k/tags/rel_13/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7988d 13h /or1k/tags/rel_13/
1010 Import ivang 7992d 16h /or1k/tags/rel_13/
1009 Import ivang 7992d 17h /or1k/tags/rel_13/
1008 Import ivang 7992d 17h /or1k/tags/rel_13/
1007 Import ivang 7992d 17h /or1k/tags/rel_13/
1006 Import ivang 7992d 17h /or1k/tags/rel_13/
1005 Import ivang 7992d 18h /or1k/tags/rel_13/
1004 Now every ramdisk image should have init program. simons 7993d 02h /or1k/tags/rel_13/
1003 cuc temporary files are deleted upon exiting markom 7993d 02h /or1k/tags/rel_13/

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